Staff Physical Design Engineer

Are you an experienced Staff Physical Design Engineer looking for your next challenge?

Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we'd love to hear from skilled professionals who are passionate about Physical Design. With design centres across the UK, Spain, Hyderabad, and Morocco, we offer the flexibility to base this role in any of our global locations. If you're interested in exploring future opportunities with us, please click the link below to apply and register your interest.

The Staff Physical Design Engineer is expected to work as part of a Physical implementation design team. Within the team the designer will have responsibility for block development and possibly full chip responsibility from RTL to GDS and will be expected to be diligent their ownership of the responsibilities assigned to them. They will also be able manage a team of 2-3 engineers of lower grade and be responsible for their line management and if appropriate day-to-day tasks.

• The person should contribute to physical design projects with little guidance and can work independently.
• Should be capable of solving problems of moderate complexity.
• Applies judgment in interpreting results and conducting quantitative analysis.
• Will be engaged in maintaining a high quality in their work.
• Should be able to take multi-assignments from different customers/Teams.
• Should be capable of interacting with the more experienced team members to resolve problems.
• Should show ability in many tools or be an expert in one or two. Examples of which are: Synthesis, PnR, Formal verification, Custom layout techniques, Analog simulation, and Chip finishing.
• Should be able to contributes to technical white papers.
• May contribute to sales support as part of a team, such as Statement of Work
• Should be capable of maintaining accurate time keeping.
• Should be self-disciplined in executing design tasks.
• Team leader of a team of 2-3 engineers or be able to train the junior engineers

A degree/masters or PhD in either a relevant subject

• Typically, 5+ years' experience
• Should have good tapeout experience on multiple technologies 3nm, 5nm,7nm,12nm,16nm, 22nm, 28nm
• Should have worked on the DRC, LVS, ANTENNA, ERC physical verification checks
• Should have good work experience and understanding of Concepts in Synthesis, Floorplaning, Placement, CTS, Routing, STA
• Input skill set one or more of the following: PnR using either Synopsys ICC, Cadence EDI, Mentor Olympus, Synthesis using either Synopsys DC or Cadence RC, Experience of Formailty or Formalpro, Experience of Mentor Calibre or Synopsys IC Validator
• Serves as an independent individual contributor to technical project
• Demonstrates capability as a problem solver with an ability to work individually or as part of a team
• Evaluates issues and defines solutions as part of a team
• Broadens cross disciplinary knowledge through new assignments

Self-organisation and ability to respond to changing priorities quickly